﻿/**
 * @file		_jmlexs.h
 * @brief		Definition JMLEXS Macro I/O register
 * @note		None
 * @attention	None
 * 
 * <B><I>Copyright 2015,2016 Socionext Inc.</I></B>
 */

#include "__jmlexs.h"

/*	Structure of XDMAC LowPower Control	(4B11_0000h)	*/
union io_exstop_xdmaclowpowctrl {
	unsigned long		word;
	struct {
		unsigned long	CSYSREQ				:1;		// CSYS Request
		unsigned long						:7;		// reserved
		unsigned long	CSYSACK				:1;		// CSYS Acknowlege
		unsigned long						:7;		// reserved
		unsigned long	CACTIVE				:1;		// C Active
		unsigned long						:15;	// reserved
    } bit;
};

/*	Structure of SoftReset	(4B11_000Ch)	*/
union io_exstop_softreset {
	unsigned long		word;
	struct {
		unsigned long	NFRSTN				:1;		// NF Reset
		unsigned long	NFRSTNBCH			:1;		// NF Reset Bch
		unsigned long	NFRSTNREG			:1;		// NF Reset Reg
		unsigned long						:5;		// reserved
		unsigned long	NETSECRST			:1;		// NETSEC Reset
		unsigned long						:7;		// reserved
		unsigned long	EMCRST				:1;		// eMMC Reset x
		unsigned long						:7;		// reserved
		unsigned long	RELCRST				:1;		// RELC Reset
		unsigned long						:7;		// reserved
    } bit;
};

/*	Structure of SoftReset 2	(4B11_0010h)	*/
union io_exstop_softreset2 {
	unsigned long		word;
	struct {
		unsigned long	DEBRSTX_reserve		:1;		// reserved
		unsigned long	DEBRSTX_SD3			:1;		// SD3( UHS2 )
		unsigned long	DEBRSTX_SD4			:1;		// SD4( UHS1 Card )
		unsigned long	DEBRSTX_PCIE0		:1;		// PCIe0
		unsigned long	DEBRSTX_PCIE1		:1;		// PCIe1
		unsigned long	DEBRSTX_USB2VBUS	:1;		// USB2 VBUS
		unsigned long	DEBRSTX_USB2ID		:1;		// USB2 ID
		unsigned long	DEBRSTX_USB3VBUS	:1;		// USB3 VBUS
		unsigned long	DEBRSTX_USB3ID		:1;		// USB3 ID
		unsigned long						:23;	// reserved
    } bit;
};

/*	Structure of INTMSK register	(4B11_0014h)	*/
union io_exstop_intmsk {
	unsigned long		word;
	struct {
		unsigned long	INTMSK00			:1;		// reserved
		unsigned long	INTMSK01			:1;		// reserved
		unsigned long	INTMSK02			:1;		// SD3 (UHS2) INT Mask(Rising Edge)
		unsigned long	INTMSK03			:1;		// SD3 (UHS2) INT Mask(Falling Edge)
		unsigned long	INTMSK04			:1;		// SD4 (UHS1 Card) INT Mask(Rising Edge)
		unsigned long	INTMSK05			:1;		// SD4 (UHS1 Card) INT Mask(Falling Edge)
		unsigned long	INTMSK06			:1;		// PCIe0 INT Mask(Rising Edge)
		unsigned long	INTMSK07			:1;		// PCIe0 INT Mask(Falling Edge)
		unsigned long	INTMSK08			:1;		// PCIe1 INT Mask(Rising Edge)
		unsigned long	INTMSK09			:1;		// PCIe1 INT Mask(Falling Edge)
		unsigned long	INTMSK10			:1;		// USB2 VBUS INT Mask(Rising Edge)
		unsigned long	INTMSK11			:1;		// USB2 VBUS INT Mask(Falling Edge)
		unsigned long	INTMSK12			:1;		// USB2 ID INT Mask(Rising Edge)
		unsigned long	INTMSK13			:1;		// USB2 ID INT Mask(Falling Edge)
		unsigned long	INTMSK14			:1;		// USB3 VBUS INT Mask(Rising Edge)
		unsigned long	INTMSK15			:1;		// USB3 VBUS INT Mask(Falling Edge)
		unsigned long	INTMSK16			:1;		// USB3 ID INT Mask(Rising Edge)
		unsigned long	INTMSK17			:1;		// USB3 ID INT Mask(Falling Edge)
		unsigned long						:14;	// reserved
    } bit;
};

/*	Structure of SIGMON register	(4B11_0018h)	*/
union io_exstop_sigmon {
	unsigned long		word;
	struct {
		unsigned long	SIGMON_reserve		:1;		// SIGMON reserved
		unsigned long	SIGMON_SD3			:1;		// SIGMON SD3( UHS2 )
		unsigned long	SIGMON_SD4			:1;		// SIGMON SD4( UHS1 Card )
		unsigned long	SIGMON_PCIE0		:1;		// SIGMON PCIe0
		unsigned long	SIGMON_PCIE1		:1;		// SIGMON PCIe1
		unsigned long	SIGMON_USB2VBUS		:1;		// SIGMON USB2 VBUS
		unsigned long	SIGMON_USB2ID		:1;		// SIGMON USB2 ID
		unsigned long	SIGMON_USB3VBUS		:1;		// SIGMON USB3 VBUS
		unsigned long	SIGMON_USB3ID		:1;		// SIGMON USB3 ID
		unsigned long						:7;		// reserved
		unsigned long	SIGMON2_reserve		:1;		// SIGMON2 reserved
		unsigned long	SIGMON2_SD3			:1;		// SIGMON2 SD3( UHS2 )
		unsigned long	SIGMON2_SD4			:1;		// SIGMON2 SD4( UHS1 Card )
		unsigned long	SIGMON2_PCIE0		:1;		// SIGMON2 PCIe0
		unsigned long	SIGMON2_PCIE1		:1;		// SIGMON2 PCIe1
		unsigned long	SIGMON2_USB2VBUS	:1;		// SIGMON2 USB2 VBUS
		unsigned long	SIGMON2_USB2ID		:1;		// SIGMON2 USB2 ID
		unsigned long	SIGMON2_USB3VBUS	:1;		// SIGMON2 USB3 VBUS
		unsigned long	SIGMON2_USB3ID		:1;		// SIGMON2 USB3 ID
		unsigned long						:7;		// reserved
    } bit;
};

/*	Structure of DEBEN register	(4B11_001Ch)	*/
union io_exstop_deben {
	unsigned long		word;
	struct {
		unsigned long	DEBEN_reserve		:1;		// DEBEN reserved
		unsigned long	DEBEN_SD3			:1;		// DEBEN SD3( UHS2 )
		unsigned long	DEBEN_SD4			:1;		// DEBEN SD4( UHS1 Card )
		unsigned long	DEBEN_PCIE0			:1;		// DEBEN PCIe0
		unsigned long	DEBEN_PCIE1			:1;		// DEBEN PCIe1
		unsigned long	DEBEN_USB2VBUS		:1;		// DEBEN USB2 VBUS
		unsigned long	DEBEN_USB2ID		:1;		// DEBEN USB2 ID
		unsigned long	DEBEN_USB3VBUS		:1;		// DEBEN USB3 VBUS
		unsigned long	DEBEN_USB3ID		:1;		// DEBEN USB3 ID
		unsigned long						:1;		// reserved
		unsigned long	SD2DETIM			:2;		// reserved
		unsigned long	SD3DETIM			:2;		// SD3( UHS2 )
		unsigned long	SD4DETIM			:2;		// SD4( UHS1 Card )
		unsigned long	PCIE0DETIM			:2;		// PCIe0
		unsigned long	PCIE1DETIM			:2;		// PCIe1
		unsigned long	USB2VBUSDETIM		:2;		// USB2 VBUS
		unsigned long	USB2IDDETIM			:2;		// USB2 ID
		unsigned long	USB3VBUSDETIM		:2;		// USB3 VBUS
		unsigned long	USB3IDDETIM			:2;		// USB3 ID
		unsigned long						:4;		// reserved
    } bit;
};

/*	Structure of CDINS MOD Control	(4B11_0020h)	*/
union io_exstop_cdimodctrl {
	unsigned long		word;
	struct {
		unsigned long	CDIMOD_reserve		:1;		// CDIMOD reserved
		unsigned long	CDIMOD_SD3			:1;		// CDIMOD SD3( UHS2 )
		unsigned long	CDIMOD_SD4			:1;		// CDIMOD SD4( UHS1 Card )
		unsigned long	CDIMOD_PCIE0		:1;		// CDIMOD PCIe0
		unsigned long	CDIMOD_PCIE1		:1;		// CDIMOD PCIe1
		unsigned long	CDIMOD_USB2VBUS		:1;		// CDIMOD USB2 VBUS
		unsigned long	CDIMOD_USB2ID		:1;		// CDIMOD USB2 ID
		unsigned long	CDIMOD_USB3VBUS		:1;		// CDIMOD USB3 VBUS
		unsigned long	CDIMOD_USB3ID		:1;		// CDIMOD USB3 ID
		unsigned long						:23;	// reserved
    } bit;
};

/*	Structure of RELC HPROT Control	(4B11_0030h)	*/
union io_exstop_relchptctrl {
	unsigned long		word;
	struct {
		unsigned long	RERHPT				:4;		// RELC R HPROT
		unsigned long						:4;		// reserved
		unsigned long	REWHPT				:4;		// RELC W HPROT
		unsigned long						:20;	// reserved
    } bit;
};

/*	Structure of RAM PD Control	(4B11_0040h)	*/
union io_exstop_rampdctrl {
	unsigned long		word;
	struct {
		unsigned long	RAMPD_SD2			:1;		// SD2( UHS1 Wifi )
		unsigned long	RAMPD_SD3			:1;		// SD3( UHS2 )
		unsigned long	RAMPD_SD4			:1;		// SD4( UHS1 Card )
		unsigned long	RAMPD_NF			:1;		// Nand Flash
		unsigned long	RAMPD_RELC			:1;		// RELC
		unsigned long	RAMPD_NETSEC		:1;		// NETSEC
		unsigned long	RAMPD_USB2			:1;		// USB2
		unsigned long	RAMPD_USB3			:1;		// USB3
		unsigned long	RAMPD_PCIE0			:1;		// PCIe0
		unsigned long	RAMPD_PCIE1			:1;		// PCIe1
		unsigned long	RAMPD_EMMC			:1;		// eMMC
		unsigned long						:21;	// reserved
    } bit;
};

/*	Structure of BUS CLOCK Stop Control	(4B11_0060h)	*/
union io_exstop_busckstpctrl {
	unsigned long		word;
	struct {
		unsigned long	NF_CKSTP			:1;		// Nand Flash
		unsigned long	PCIE0_CKSTP			:1;		// PCIe0
		unsigned long	PCIE1_CKSTP			:1;		// PCIe1
		unsigned long	XDMAC_CKSTP			:1;		// XDMAC
		unsigned long	HDMAC_CKSTP			:1;		// HDMAC
		unsigned long	EMMC_CKSTP			:1;		// eMMC
		unsigned long	SD2_CKSTP			:1;		// SD2( Wifi )
		unsigned long	SD3_CKSTP			:1;		// SD3( UHS2 )
		unsigned long	SD4_CKSTP			:1;		// SD4( UHS1 Card )
		unsigned long	NETSEC_CKSTP		:1;		// NETSEC
		unsigned long	RELC_CKSTP			:1;		// RELC
		unsigned long						:21;	// reserved
    } bit;
};

/*	Structure of NETSEC PTPCLK Stop Control	(4B11_0070h)	*/
union io_exstop_netsecptpclkstopctrl {
	unsigned long		word;
	struct {
		unsigned long	NETSECPTPSTP		:1;		// NETSEC PTP_CLK Stop Control
		unsigned long						:31;	// reserved
    } bit;
};

/*	Structure of EMMC_CKSTP register	(4B11_0074h)	*/
union io_exstop_emmcckstp {
	unsigned long		word;
	struct {
		unsigned long	EMCLKSTP			:1;		// MMC_BCLK_I Control
		unsigned long						:31;	// reserved
    } bit;
};

/*	Structure of EM_DRVSTR register	(4B11_0090h)	*/
union io_exstop_emdrvstr {
	unsigned long		word;
	struct {
		unsigned long	EM_DSEL				:2;		// EM_DSEL
		unsigned long						:30;	// reserved
    } bit;
};

/*	Structure of EM_PV_DTIMEC register	(4B11_00B4h)	*/
union io_exstop_empvdtimec {
	unsigned long		word;
	struct {
		unsigned long	PV_DTIMEC			:24;	// PV_DTIMEC
		unsigned long						:8;		// reserved
    } bit;
};

/*	Structure of EM_PV_AMPBL register	(4B11_00B8h)	*/
union io_exstop_empvampbl {
	unsigned long		word;
	struct {
		unsigned long	PV_AMPBL			:4;		// PV_AMPBL
		unsigned long						:28;	// reserved
    } bit;
};

/*	Structure of EM_CR_SLOTTYPE register	(4B11_00BCh)	*/
union io_exstop_emcrslottype {
	unsigned long		word;
	struct {
		unsigned long	CR_SLOTTYPE			:1;		// CR_SLOTTYPE
		unsigned long						:31;	// reserved
    } bit;
};

/*	Structure of EM_CR_BCLKFREQ register	(4B11_00C0h)	*/
union io_exstop_emcrbclkfreq {
	unsigned long		word;
	struct {
		unsigned long	CR_BCLKFREQ			:8;		// CR_BCLKFREQ
		unsigned long						:24;	// reserved
    } bit;
};

/*	Structure of EM_CDDET register	(4B11_00C4h)	*/
union io_exstop_emcddet {
	unsigned long		word;
	struct {
		unsigned long	EMCD				:1;		// EMCD
		unsigned long						:7;		// reserved
		unsigned long	EMPHYLK				:1;		// EMPHYLK
		unsigned long						:23;	// reserved
    } bit;
};

/*	Structure of NF_IP_CTL register	(4B11_0300h)	*/
union io_exstop_nfipctl {
	unsigned long		word;
	struct {
		unsigned long	DSCV_INHIBIT		:1;		// Nand Flash IP ( cdns_hpnfc ) discovery_inhibit Control
		unsigned long	DSCV_IGNR_CRC		:1;		// Nand Flash IP ( cdns_hpnfc ) discovery_ignore_crc Control
		unsigned long						:2;		// reserved
		unsigned long	BOOT_EN				:1;		// Nand Flash IP ( cdns_hpnfc ) boot_en Control
		unsigned long						:3;		// reserved
		unsigned long	IDDQ_EN				:1;		// Nand Flash IP ( cdns_flash_dll_phy ) iddq_en Control
		unsigned long						:23;	// reserved
    } bit;
};

/*	Structure of NF_BTSQ_STATE register	(4B11_0304h)	*/
union io_exstop_nfbtsqstate {
	unsigned long		word;
	struct {
		unsigned long	INIT_FAIL			:1;		// Nand Flash IP ( cdns_hpnfc ) init_fail monitor
		unsigned long						:3;		// reserved
		unsigned long	BOOT_COMP			:1;		// Nand Flash IP ( cdns_hpnfc ) boot_comp monitor
		unsigned long						:3;		// reserved
		unsigned long	BOOT_ERROR			:1;		// Nand Flash IP ( cdns_hpnfc ) boot_error monitor
		unsigned long						:3;		// reserved
		unsigned long	CTRL_BUSY			:1;		// Nand Flash IP ( cdns_hpnfc ) ctrl_busy monitor
		unsigned long						:19;	// reserved
    } bit;
};

/*	Structure of NF_RB_VALID_TM register	(4B11_0308h)	*/
union io_exstop_nfbvalidtm {
	unsigned long		word;
	struct {
		unsigned long	RB_VALID_TIME		:16;	// Nand Flash IP ( cdns_hpnfc ) rb_valid_time[15:0] Control
		unsigned long						:16;	// reserved
    } bit;
};

/*	Structure of NF_PHY_CTRL_REG register	(4B11_030Ch)	*/
union io_exstop_nfphyctrlreg {
	unsigned long		word;
	struct {
		unsigned long	PHY_CTRL			:32;	// Nand Flash IP ( cdns_hpnfc )  phy_ctrl_reg[31:0] Control
    } bit;
};

/*	Structure of NF_PHY_DQ_TIM register	(4B11_0310h)	*/
union io_exstop_nfphydqtim {
	unsigned long		word;
	struct {
		unsigned long	PHY_DQ_TIMING		:32;	// Nand Flash IP ( cdns_hpnfc )  phy_dq_timing[31:0] Control
    } bit;
};

/*	Structure of NF_PHY_DQS_TIM register	(4B11_0314h)	*/
union io_exstop_nfphydqstim {
	unsigned long		word;
	struct {
		unsigned long	PHY_DQS_TIMING		:32;	// Nand Flash IP ( cdns_hpnfc )  phy_dqs_timing[31:0] Control
    } bit;
};

/*	Structure of NF_PHY_GT_LPBK register	(4B11_0318h)	*/
union io_exstop_nfphygtlpbk {
	unsigned long		word;
	struct {
		unsigned long	PHY_GT_LPBK_CTL		:32;	// Nand Flash IP ( cdns_hpnfc )  phy_gate_lpbk_ctrl_reg[31:0] Control
    } bit;
};

/*	Structure of NF_PHY_DLL_MCTL register	(4B11_031Ch)	*/
union io_exstop_nfphydllmctl {
	unsigned long		word;
	struct {
		unsigned long	PHY_DLL_MST_CTL		:32;	// Nand Flash IP ( cdns_hpnfc )  phy_dll_master_ctrl_reg[31:0] Control
    } bit;
};

/*	Structure of NF_PHY_DLL_SCTL register	(4B11_0320h)	*/
union io_exstop_nfphydllsctl {
	unsigned long		word;
	struct {
		unsigned long	PHY_DLL_SLV_CTL		:32;	// Nand Flash IP ( cdns_hpnfc )  phy_dll_slave_ctrl_reg[31:0] Control
    } bit;
};

/*	Structure of NF_BOOT_ECC_CTL register	(4B11_0324h)	*/
union io_exstop_nfbooteccctl {
	unsigned long		word;
	struct {
		unsigned long	BOOT_ECC_SEC_SIZ	:16;	// Nand Flash IP ( cdns_hpnfc )  boot_ecc_sec_size[15:0] Control
		unsigned long	BT_ECC_CORR_STR		:3;		// Nand Flash IP ( cdns_hpnfc )  boot_ecc_corr_str[2:0] Control
		unsigned long						:5;		// reserved
		unsigned long	BOOT_ECC_EN			:1;		// Nand Flash IP ( cdns_hpnfc )  boot_ecc_enable Control
		unsigned long						:7;		// reserved
    } bit;
};

/*	Structure of NF_NFWPX_CNT register	(4B11_0328h)	*/
union io_exstop_nfnfwpxcnt {
	unsigned long		word;
	struct {
		unsigned long	NFWPX_CNT			:1;		// NFWPX mask control
		unsigned long						:31;	// reserved
    } bit;
};

/*	Structure of INTSTAT register	(4B11_0F00h)	*/
union io_exstop_intstat {
	unsigned long		word;
	struct {
		unsigned long	__INTSTAT00			:1;		// SD2 (UHS1 Wifi) rising edge detection
		unsigned long	__INTSTAT01			:1;		// SD2 (UHS1 Wifi) falling edge detection
		unsigned long	__INTSTAT02			:1;		// SD3 (UHS2) rising edge detection
		unsigned long	__INTSTAT03			:1;		// SD3 (UHS2) falling edge detection
		unsigned long	__INTSTAT04			:1;		// SD4 (UHS1 Card) rising edge detection
		unsigned long	__INTSTAT05			:1;		// SD4 (UHS1 Card) falling edge detection
		unsigned long	__INTSTAT06			:1;		// PCIe0 rising edge detection
		unsigned long	__INTSTAT07			:1;		// PCIe0 falling edge detection
		unsigned long	__INTSTAT08			:1;		// PCIe1 rising edge detection
		unsigned long	__INTSTAT09			:1;		// PCIe1 falling edge detection
		unsigned long	__INTSTAT10			:1;		// USB2 VBUS rising edge detection
		unsigned long	__INTSTAT11			:1;		// USB2 VBUS falling edge detection
		unsigned long	__INTSTAT12			:1;		// USB2 ID rising edge detection
		unsigned long	__INTSTAT13			:1;		// USB2 ID falling edge detection
		unsigned long	__INTSTAT14			:1;		// USB3 VBUS rising edge detection
		unsigned long	__INTSTAT15			:1;		// USB3 VBUS falling edge detection
		unsigned long	__INTSTAT16			:1;		// USB3 ID rising edge detection
		unsigned long	__INTSTAT17			:1;		// USB3 ID falling edge detection
		unsigned long						:14;	// reserved
    } bit;
};

struct io_exstop {
	union io_exstop_xdmaclowpowctrl			XDMACLPCTRL;							/*	4B11_(0000 - 0003h)	*/
	unsigned char							dmy_exstop_0004_000B[0x000C-0x0004];	/*	4B11_(0004 - 000Bh)	*/
	union io_exstop_softreset				SOFTRESET;								/*	4B11_(000C - 000Fh)	*/
	union io_exstop_softreset2				SOFTRESET2;								/*	4B11_(0010 - 0013h)	*/
	union io_exstop_intmsk					INTMSK;									/*	4B11_(0014 - 0017h)	*/
	union io_exstop_sigmon					SIGMON;									/*	4B11_(0018 - 001Bh)	*/
	union io_exstop_deben					DEBEN;									/*	4B11_(001C - 001Fh)	*/
	union io_exstop_cdimodctrl				CDINSMDCTL;								/*	4B11_(0020 - 0023h)	*/
	unsigned char							dmy_exstop_0024_002F[0x0030-0x0024];	/*	4B11_(0024 - 002Fh)	*/
	union io_exstop_relchptctrl				RLC_HPT_CTL;							/*	4B11_(0030 - 0033h)	*/
	unsigned char							dmy_exstop_0034_003F[0x0040-0x0034];	/*	4B11_(0034 - 003Fh)	*/
	union io_exstop_rampdctrl				RAM_PD;									/*	4B11_(0040 - 0043h)	*/
	unsigned char							dmy_exstop_0044_005F[0x0060-0x0044];	/*	4B11_(0044 - 005Fh)	*/
	union io_exstop_busckstpctrl			BUSCKSTP;								/*	4B11_(0060 - 0063h)	*/
	unsigned char							dmy_exstop_0064_006F[0x0070-0x0064];	/*	4B11_(0064 - 006Fh)	*/
	union io_exstop_netsecptpclkstopctrl	NSEC_CKSTP;								/*	4B11_(0070 - 0073h)	*/
	union io_exstop_emmcckstp				EMMC_CKSTP;								/*	4B11_(0074 - 0077h)	*/
	unsigned char							dmy_exstop_0078_008F[0x0090-0x0078];	/*	4B11_(0078 - 008Fh)	*/
	union io_exstop_emdrvstr				EM_DRVSTR;								/*	4B11_(0090 - 0093h)	*/
	unsigned char							dmy_exstop_0094_00B3[0x00B4-0x0094];	/*	4B11_(0094 - 00B3h)	*/
	union io_exstop_empvdtimec				EM_PV_DTIMEC;							/*	4B11_(00B4 - 00B7h)	*/
	union io_exstop_empvampbl				EM_PV_AMPBL;							/*	4B11_(00B8 - 00BBh)	*/
	union io_exstop_emcrslottype			EM_CR_SLOTTYPE;							/*	4B11_(00BC - 00BFh)	*/
	union io_exstop_emcrbclkfreq			EM_CR_BCLKFREQ;							/*	4B11_(00C0 - 00C3h)	*/
	union io_exstop_emcddet					EM_CDDET;								/*	4B11_(00C4 - 00C7h)	*/
	unsigned char							dmy_exstop_00C8_02FF[0x0300-0x00C8];	/*	4B11_(00C8 - 02FFh)	*/
	union io_exstop_nfipctl					NF_IP_CTL;								/*	4B11_(0300 - 0303h)	*/
	union io_exstop_nfbtsqstate				NF_BTSQ_STATE;							/*	4B11_(0304 - 0307h)	*/
	union io_exstop_nfbvalidtm				NF_RB_VALID_TM;							/*	4B11_(0308 - 030Bh)	*/
	union io_exstop_nfphyctrlreg			NF_PHY_CTRL_REG;						/*	4B11_(030C - 030Fh)	*/
	union io_exstop_nfphydqtim				NF_PHY_DQ_TIM;							/*	4B11_(0310 - 0313h)	*/
	union io_exstop_nfphydqstim				NF_PHY_DQS_TIM;							/*	4B11_(0314 - 0317h)	*/
	union io_exstop_nfphygtlpbk				NF_PHY_GT_LPBK;							/*	4B11_(0318 - 031Bh)	*/
	union io_exstop_nfphydllmctl			NF_PHY_DLL_MCTL;						/*	4B11_(031C - 031Fh)	*/
	union io_exstop_nfphydllsctl			NF_PHY_DLL_SCTL;						/*	4B11_(0320 - 0323h)	*/
	union io_exstop_nfbooteccctl			NF_BOOT_ECC_CTL;						/*	4B11_(0324 - 0327h)	*/
	union io_exstop_nfnfwpxcnt				NF_NFWPX_CNT;							/*	4B11_(0328 - 032Bh)	*/
	unsigned char							dmy_exstop_032C_0EFF[0x0F00-0x032C];	/*	4B11_(032C - 0EFFh)	*/
	union io_exstop_intstat					INTSTAT;								/*	4B11_(0F00 - 0F03h)	*/
	unsigned char							dmy_exstop_0F04_FFFF[0x10000-0x0F04];	/*	4B11_(0F04 - FFFFh)	*/
};

extern volatile struct io_exstop IO_EXSTOP;		// address 4B11_0000h - 

